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Universal Cordless Telephone Subsystem IC
The MC13109A integrates several of the functions required for a cordless telephone into a single integrated circuit. This significantly reduces component count, board space requirements, and external adjustments. It is designed for use in both the handset and the base. * Dual Conversion FM Receiver - Complete Dual Conversion Receiver - Antenna Input to Audio Output 80 MHz Maximum Carrier Frequency - RSSI Output - Carrier Detect Output with Programmable Threshold - Comparator for Data Recovery - Operates with Either a Quad Coil or Ceramic Discriminator
MC13109A
UNIVERSAL CT-0 SUBSYSTEM INTEGRATED CIRCUIT
* *
52
1
Compander - Expandor Includes Mute, Digital Volume Control and Speaker Driver - Compressor Includes Mute, ALC and Limiter Dual Universal Programmable PLL - Supports New 25 Channel U.S. Standard with No External Switches - Universal Design for Domestic and Foreign CT-0 Standards - Digitally Controlled Via a Serial Interface Port - Receive Side Includes 1st LO VCO, Phase Detector, and 14-Bit Programmable Counter and 2nd LO with 12-Bit Counter - Transmit Section Contains Phase Detector and 14-Bit Counter - MPU Clock Output Eliminates Need for MPU Crystal Supply Voltage Monitor - Externally Adjustable Trip Point 2.0 to 5.5 V Operation with One-Third the Power Consumption of Competing Devices
FB SUFFIX PLASTIC PACKAGE CASE 848B (QFP-52)
48
1
* *
FTA SUFFIX PLASTIC PACKAGE CASE 932 (LQFP-48)
ORDERING INFORMATION
Device MC13109AFB MC13109AFTA Tested Operating Temperature Range TA = -20 to 85C Package QFP-52 LQFP-48
Simplified Block Diagram
Rx In
1st Mixer
2nd Mixer
Limiting IF Amplifier
Detector
1st LO PLL Carrier Detect Tx In Tx Out Tx VCO Tx Phase Detector Mute Compressor
2nd LO PLL
RSSI
Mute Expander
Rx Out Data Out P Serial Interface SPI Low Battery Indicator
Low Battery Detect This device contains 6,609 active transistors.
(c) Motorola, Inc. 1999
Rev 1
MOTOROLA RF/IF DEVICE DATA
1
MC13109A
Figure 1. MC13109AFB Test Circuit
Rx_Audio Ext_C_In VCCE R32 100k VCC/2 R31 100k C43 0.1F Open C47 MIC_ 1.0F Amp R28 Out 49.9k C38 5.0nF Open LO1 C40 1.0F Mix1_In VCC R27 49.9k 50 C36 0.01F In 2 3 Mix1 In1 Out CF1 10.7 MHz 1 2 3 1 Tx_In L1
Ext_Ref R29 49.9k R30 49.9k VCCA
Open C35 0.01F
C30 1.0F
C41 C42 0.47 5.0nF F
330
XL1 R34 1.5k R35 32.4k C45 0.1F R33 3.0k C3 0.047F R1 1.5k C5 0.1F R2 32.4k R3 32.4k C6 0.022F VCCA Tx_VCO C48 1.0F Ext C14 1.0F R8 100k C2 4.3pF 10.24 MHz C44 10F
2nd LO 10.240
R x Phase Detect
C4 0.01F
14b Prog Rx Ctr
LO2 Out 2 PLL Vref 3 Rx PD 4 Gnd PLL 5 Tx PD 6 Ecap Tx VCO Data 9 EN 10 Clk 11 Clk Out 12 N/A 13 7 8
2nd LO 12b Prog Ref Ctr
+- Spl Amp
Tx Mute
+-
1st LO VCO
1
VB
VB
39
Gnd Out
Mix1 In2 38 37 36 35 34 2nd Mix 33 32 Mix1 Out VB Mix2 In Mix2 Out Gnd RF Lim In C32 0.1F C31 0.1F VCC C30 0.1F C29 10F R24 10 R23 1.5k C34 1.0F
ALC 1st LO Compressor Limiter Half Supply Reference 2nd LO
1st Mix
/1 /4 /25
CF2 Ext_IF
1st LO
T x Phase Detect
PLL Vref 14b Prog Tx Ctr Bandgap Reference 2.2V Voltage Regulator IF Amp/ Limiter Carrier Detect RSSI Expander VB E + - Spkr Cap Mute Spkr Amp Data Amp
C33 0.1F R23 10.2
P Serial Interface
R4 100k C7 15pF
31 Lim C1 Lim C2 30 29 VCC RF Q Coil N/A 27
455k In
1N5140 C8 18pF
Ref
Prog Clk Ctr
Low Battery Detect
Detector
Rx Mute Pre- Amp
L2 C28 0.1F R22 12k C27 0.1F TOKO A7MES-12597Z
28
L3 0.22H C9 33pF R5 22.1k C11 47pF Q1 MPS5179 R6 1.0k C10 68pF R7 22.1k VCC C13 0.01 F C12 33pF Open U1 13 12 14 DA DB VCC Gnd LS09 7 Open Out 11
14 CD Status Out Out/ Hardware Interrupt Data_5.0 V
15
C15 10pF
VB 17 18 19 20 21 22 23 24 25 26 BD DA SA SA E VCC DA Pre- Rx Det RSSI Out Out Out In Out Audio In Amp Audio Out Out In C16 R13 510 R12 3.9k pF 100k R15 C24 49.9k 510pF VCCD 16
Vol Ctrl
+
-
R20 49.9k R19 49.9k C25 1.0F
R21 8.2k Det_Out C26 0.01F
Pre_Amp DA_Fil EN_5.0V DA_In
Audio_In_In C21 0.033F C22 0.1F R17 5.62k C23 0.001F R18 20k
Data_5.0V 10 9 EN_5.0V 14
DA DB
U1 Out 8 R9 1.0k R16 49.9k C18 1.0F VCCA
C19 10F
C20 0.1F
VCC Gnd 7 LS09 VCCE
Clk_5.0V Open R11 1.0k R10 1.0k Clk_5.0V U1 DA Out 6 DB VCC Gnd 7 LS09
4 5 14
E_Out Ext_SA_In C17 47F Exp_IF
1 2
DA DB
U1 Out 3 R14 130
Gnd V 7 14 CC LS09 5.0V
SA_Out
2
MOTOROLA RF/IF DEVICE DATA
CF2 455 MHz
0.0047 F
R36 22.1k C46
C1 9-35pF
LO2 In
Spl Tx Amp Lim C Amp Tx Gnd Vcap LO1 LO1 In Out Cap C In Out In Audio Ctrl Out In N/A Ref Out 52 51 50 49 48 47 46 45 44 43 42 41 40
In
MC13109A
Figure 2. MC13109AFTA Test Circuit
Rx_Audio Tx_In Open VCCE R32 100k R31 100k MIC_ Amp Out R29 49.9k C42 5.0nF C43 0.1F Tx Ref Out 48 47 1 2nd LO 10.240 2 3 4 5 6 R3 32.4k C6 0.022F VCCA Tx_VCO T x Phase Detect E Cap Tx C48 1.0F VCO Data 9 C14 1.0 F VCC R8 100k EN 10 Clk Clk Out Prog Clk Ctr 11 12 13 CD Out/ Hardware Interrupt C13 0.01 F BD Out 14 DA Out R13 3.9k R12 100k VCC 5.0V 13 DA 12 DB U1 Out 11 Open R14 130 VCCD 15 SA Out P Serial Interface Ref E + - Spkr Cap Mute Spkr Amp 16 SA In C16 510pF R15 49.9k C17 47F 17 VB 7 8 R4 100k C7 15pF Ext 2nd LO VB +- Spl Amp Tx Mute ALC Compressor Limiter 14b Prog R x Ctr Half Supply Reference 2nd LO 2nd Mix Spl Amp In 46 R30 49.9k C30 1.0F VCCA C40 1.0F C38 5.0nF Open C41 0.47 F C Cap 45 44 R27 49.9k LO1 Mix1_In Ext_C_In C47 1.0F R28 49.9k
VCC/2 Ext_Ref
L1
Open
R36 22.1k
C46 0.0047 F
R35 32.4k C45 0.1F C1 9-35pF 10.24 MHz C2 4.3pF C44 10F
Lim Out
R34 1.5k
XL1
LO2 In LO2 Out PLL Vref Rx PD Gnd PLL
Amp Out C In 43 42
Tx Gnd Vcap LO1 LO1 In Audio In Ctrl Out 41 40 39 38 37 VB +- 1st LO VCO 36 35 34 33 32 31 30 Mix1 In1 50 C36 0.01F Mix1 In2 C35 0.01F VCC 330 Mix2 In Mix2 Out Gnd RF CF2 1 In 2 Gnd 3 Out In 2 3 Out CF1 10.7 MHz CF2 455 MHz VCC Mix1 Out C34 1.0F VB 1
R33 3.0k C3 0.047F
C4 0.01F
12b Prog Ref Ctr R x Phase Detect /1 /4 /25
1st Mix 1st LO
C5 0.1F
R2 32.4k
R1 1.5k
Tx PD
1st LO
PLL Vref 14b Prog Tx Ctr 2.2V Voltage Regulator Bandgap Reference Carrier Detect RSSI Expander Data Amp Vol Ctrl 20 DA In Pre- Amp Out 21 + VB 22 23 24 Rx Det RSSI Audio Out In C24 510pF R19 49.9k R20 49.9k C25 1.0F - 25 Rx Mute Detector Pre- Amp IF Amp/ Limiter 29
Lim In Lim C1 28 Lim C2 27 26 VCC RF Q Coil C30 0.1F C29 10F C32 0.1F C31 0.1F Ext_IF R23 1.5k R24 10 C33 0.1F
455k In
1N5140 C8 18pF L3 0.22H R5 22.1k C11 47pF R6 1.0k C12 33pF C9 33pF C10 68pF Q1
R23 10.2
Low Battery Detect
R7 22.1k
18 19 E VCC Out Audio
C27 0.1F
Det_Out R22 12k
MPS5179
C15 10pF
R21 8.2k
C26 0.01F
L2 TOKO A7MES-12597Z Audio_In_In C28 0.1F
Pre_Amp
14 V Gnd 7 CC LS09 Data_5.0V 10 U1 DA Out 8 Open
Data_ 5.0 V
EN_5.0V VCCE
SA_Out
DA_Fil
C22 0.1F R17 5.62k C21 0.033F
R18 20k
Clk_5.0 V R9 1.0k R10 1.0k Open R16 49.9k C18 1.0F
VCCA C19 10F C20 0.1F
DA_In
9 DB 14 Gnd 7 VCC LS09 EN_5.0V
C23 0.001F
R11 1.0k
4 DA U1 Out 6 5 DB 14 Gnd VCC LS09 7 Clk_5.0V 1 2 U1 DA Out 3 Exp_IF E_Out Ext_SA_In
DB 14 V Gnd 7 CC LS09
MOTOROLA RF/IF DEVICE DATA
3
MC13109A
MAXIMUM RATINGS
AAA A A A AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAA A AA
Power Supply Voltage Junction Temperature VCC TJ - 0.5 to + 5.5 - 65 to +150 Vdc C
NOTES: 1. Devices should not be operated at or outside these limits. The "Recommended Operating Conditions" table provides for actual device operation. 2. ESD data available upon request. 3. Meets Human Body Model (HBM) 2000V and Machine Model (MM) 200V.
Rating
Symbol
Value
Unit
RECOMMENDED OPERATING CONDITIONS
Characteristic Min 2.0 -20 Typ - - Max 5.5 85 Unit Vdc C
VCC
Operating Ambient Temperature
NOTE: All limits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (VCC = 2.6 V, TA = 25C, RF In = 46.61 MHz,
fDEV = 3.0 kHz, fmod = 1.0 kHz; Test Circuit Figure 1.) Characteristic POWER SUPPLY Static Current Active Mode (VCC = 2.6 V) Active Mode (VCC = 3.6 V) Receive Mode (VCC = 2.6 V) Receive Mode (VCC = 3.6 V) Standby Mode (VCC = 2.6 V) Standby Mode (VCC = 3.6 V) Inactive Mode (VCC = 2.6 V) Inactive Mode (VCC = 3.6 V) Min Typ Max Unit
- - - - - - - -
6.1 6.5 3.9 4.3 320 550 40 54
12 - 7.0 - 600 - 80 -
mA mA mA mA A A A A
4
MOTOROLA RF/IF DEVICE DATA
MC13109A
ELECTRICAL CHARACTERISTICS (continued) FM Receiver The FM receivers can be used with either a quad coil or a ceramic resonator. The FM receiver and 1st LO have been designed to work for all country channels, including 25 channel U.S., without the need for any external switching circuitry (see Figure 25.)
(Test Conditions: VCC = 2.6 V, TA = 25C, fO = 46.61 MHz, fDEV = 3.0 kHz, fmod = 1.0 kHz.) Characteristic Sensitivity (Input for 12 dB SINAD) 1st Mixer Voltage Conversion Gain 2nd Mixer Voltage Conversion Gain 1st Mixer Input Impedance 2nd Mixer Input Impedance 1st Mixer Output Impedance 2nd Mixer Output Impedance 1st and 2nd Mixer Voltage Gain Total IF - 3.0 dB Limiting Sensitivity Total Harmonic Distortion (CCITT Filter) Recovered Audio Condition Matched Impedance Differential Input Vin = 1.0 mVrms, with CF1 as Load Vin = 3.0 mVrms, with CF2 as Load - - - - Vin = 1.0 mVrms, with CF1 and CF2 as Load fin = 455 kHz With RC = 8.2 k/ 0.01 F Filter at Det Out With RC = 8.2 k/ 0.01 F Filter at Det Out - Vin = 10 mVrms, RC = 8.2 k/0.01 F 30% AM, Vin = 10 mVrms, RC = 8.2 k/0.001 F Matched Impedance Input Matched Impedance Input - Input Pin Mix1 In1/2 Mix1 In1/2 Mix2 In - - - - Mix1 In1/2 Lim In Mix1 In1/2 Mix1 In1/2 Lim In Mix1 In1/2 Mix1 In1/2 Mix1 In1/2 Mix2 In Measure Pin Det Out Mix1 Out Mix2 Out Mix1 In1 Mix1 In2 Mix2 In Mix1 Out Mix2 Out Mix2 Out Det Out Det Out Symbol VSIN MXgain1 MXgain2 RP1 CP1 RP2 CP2 RP1 Out CP1 Out RP2 Out CP2 Out MXgainT IF Sens THD Min - - - - - - - 24 - - Typ 0.7 10 20 0.88 2.5 3.0 2.7 390 1.8 1.5 12 27 55 1.0 Max - - - - - - - - 100 3.0 Unit Vrms dB dB k pF k pF pF k pF dB Vrms %
Det Out
AFO
80
100
154
mVrms
Demodulator Bandwidth Signal to Noise Ratio AM Rejection Ratio
Det Out Det Out Det Out
BW SN AMR
- - 30
20 50 40
- - -
kHz dB dB
First Mixer 3rd Order Intercept (Input Referred) Second Mixer 3rd Order Intercept (Input Referred) Detector Output Impedance
Mix1 Out
TOImix1
-
-10
-
dBm
Mix2 Out
TOImix2
-
- 27
-
dBm
-
Det Out
ZO
-
870
-
MOTOROLA RF/IF DEVICE DATA
5
MC13109A
ELECTRICAL CHARACTERISTICS (continued) RSSI/Carrier Detect Connect 0.01 F to Gnd from "RSSI" output pin to form the carrier detect filter. "CD Out" is an open collector output which requires an external 100 k pull-up resistor to VCC.
(RL = 100 k, VCC = 2.6 V, TA = 25C.) Characteristic RSSI Output Current Dynamic Range Carrier Sense Threshold Hysteresis Output High Voltage Output Low Voltage Carrier Sense Threshold Adjustment Range Carrier Sense Threshold - Number of Steps Condition - CD Threshold Adjust = (10100) - Vin = 0 Vrms, RL = 100 k, CD = (10100) Vin = 100 Vrms, RL = 100 k, CD = (10100) Programmable through MPU Interface Programmable through MPU Interface Input Pin Mix1 In Mix1 In Mix1 In Mix1 In Mix1 In - - Measure Pin RSSI CD Out CD Out CD Out CD Out - - Symbol RSSI VT Hys VOH VOL VTrange VTn Min - - - - - - 20 - Typ 65 11 1.5 2.6 0.01 - 32 Max - - - - 0.4 11 - Unit dB mVrms dB V V dB -
The carrier detect threshold is programmable through the MPU interface.
Data Amp Comparator Inverting hysteresis comparator. Open collector output with internal 100 k pull-up resistor. A band pass filter is connected between the "Det Out" pin and the "DA In" pin with
(VCC = 2.6 V, TA = 25C) Characteristic Hysteresis Threshold Voltage Input Impedance Output Impedance Output High Voltage Output Low Voltage Condition - - - - Vin = VCC - 1.0 V, IOH = 0 mA Vin = VCC - 0.4 V, IOL = 0 mA Input Pin DA In DA In - - DA In DA In
component values as shown in the attached block diagram. The "DA In" input signal is ac coupled.
Measure Pin DA Out DA Out DA In DA Out DA Out DA Out
Symbol Hys VT ZI ZO VOH VOL
Min 30 VCC - 0.9 - - VCC - 0.1 -
Typ 40 VCC - 0.7 12 104 2.6 0.04
Max 50 VCC - 0.5 - - - 0.4
Unit mV V k k V V
6
MOTOROLA RF/IF DEVICE DATA
MC13109A
ELECTRICAL CHARACTERISTICS (continued) Pre-Amplifier/Expander/Rx Mute/Volume Control The Pre-Amplifier is an inverting rail-to-rail output swing operational amplifier with the non-inverting input terminal connected to the internal VB half supply reference. External resistors and capacitors can be connected to set the gain and frequency response. The expander analog ground is set to the half supply reference so the input and output swing capability will increase as the supply voltage increases. The volume control can be adjusted through the MPU interface. The "Rx Audio In" input signal is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25C, fin = 1.0 kHz, Set External Pre-Amplifier R's for Gain of 1, Volume Control = (0111).) Characteristic Pre-Amp Open Loop Gain Pre-Amp Gain Bandwidth Pre-Amp Maximum Output Swing Expander 0 dB Gain Level Expander Gain Tracking Condition - - RL = 10 k Vin = -10 dBV Vin = -20 dBV, Output Relative to G Vin = -30 dBV, Output Relative to G Vin = -10 dBV Increase input voltage until output voltage THD = 5%, then measure output voltage. RL = 10 k Ecap = 1.0 F, Rfilt = 20 k (See Appendix B) Ecap = 1.0 F, Rfilt = 20 k (See Appendix B) V (Rx Audio In) = 0 Vrms, Vin = -10 dBV Vin = -10 dBV No popping detectable during Rx Mute transitions Programmable through MPU Interface Programmable through MPU Interface Input Pin Rx Audio In Rx Audio In Rx Audio In Rx Audio In Rx Audio In Measure Pin Pre-Amp Pre-Amp Pre-Amp E Out E Out Symbol AVOL GBW VOmax G Gt Min - - - -3.0 -21 -42 Rx Audio In Rx Audio In E Out E Out THD VOmax - - Typ 60 100 VCC - 0.3 -0.3 -19.84 -40.12 0.2 -5.0 Max - - - 3.0 -19 -37 - - % dBV Unit dB kHz Vpp dB dB
Total Harmonic Distortion Maximum Output Voltage
Attack Time
Rx Audio In Rx Audio In C In
E Out
ta
-
3.0
-
ms
Release Time
E Out
tr
-
13.5
-
ms
Compressor to Expander Crosstalk Rx Mute
E Out
CT
-
-76
-
dB
Rx Audio In
E Out
Me
-
-65
-
dB
Volume Control Range Volume Control Steps
- -
- -
VCrange VCn
-14 -
- 16
16 -
dB -
MOTOROLA RF/IF DEVICE DATA
7
MC13109A
ELECTRICAL CHARACTERISTICS (continued) Speaker Amplifier/SP Mute The Speaker Amplifier is an inverting rail-to-rail operational amplifier. The non-inverting input terminal is connected to the internal VB half supply reference. External resistors and capacitors are used to set the gain and frequency response. The "SA In" input is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25C, fin = 1.0 kHz, External Resistors Set for Gain of 1.) Characteristic Maximum Output Swing Condition VCC = 2.3 V, RL = 130 VCC = 2.3 V, RL = 600 VCC = 3.4 V, 34 V RL = 600 Vin = -20 dBV RL = 130 No popping detectable during SP Mute transitions Input Pin SA In Measure Pin SA Out Symbol VOmax Min - - - SA In SA Out Msp - Typ 0.8 2.0 3.0 30 -67 Max - - - - dB Unit Vpp
SP Mute
Mic Amplifier The Mic Amplifier is an inverting rail-to-rail output operational amplifier with the non-inverting input terminal connected to the internal VB half supply reference. External
resistors and capacitors are connected to set the gain and frequency response. The "Tx In" input is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25C, fin = 1.0 kHz, External Resistors Set for Gain of 1.) Characteristic Open Loop Gain Gain Bandwidth Maximum Output Swing Condition - - RL = 10 k Input Pin Tx In Tx In Tx In Measure Pin Amp Out Amp Out Amp Out Symbol AVOL GBW VOmax Min - - - Typ 60 100 VCC - 0.3 Max - - - Unit dB kHz Vpp
8
MOTOROLA RF/IF DEVICE DATA
MC13109A
ELECTRICAL CHARACTERISTICS (continued) Compressor/ALC/Tx Mute/Limiter The compressor analog gound is set to the half supply reference so the input and output swing capability will increase as the supply voltage increases. The "C In" input is ac coupled. The ALC (Automatic Level Control) provides a soft limit to the output signal swing as the input voltage
(Test Conditions: VCC = 2.6 V, fin = 1.0 kHz, TA = 25C.) Characteristic Compressor 0 dB Gain Level Compressor Gain Tracking Condition Vin = -10 dBV, ALC disabled, Limiter disabled Vin = -30 dBV, Output Relative to G Vin = -50 dBV, Output Relative to G Maximum Compressor Gain Total Harmonic Distortion Input Impedance Attack Time Vin -70 dBV Vin -10 dBV, ALC disabled, Limiter disabled - Ccap = 1.0 F, Rfilt = 20 k (see Appendix B) Ccap = 1.0 F, Rfilt = 20 k (see Appendix B) V (C In) = 0 Vrms, Vin = -10 dBV Vin = -10 dBV, ALC disabled No popping detectable during Rx Mute transitions - Vin = -18 dBV Vin = -2.5 dBV ALC disabled C In C In Lim Out Lim Out AVmax THD Input Pin C In Measure Pin Lim Out Symbol G Min -3.0 Typ -0.06 Max 3.0 Unit dB
increases slowly (i.e., a sine wave is maintained). The Limiter circuit limits rapidly changing signal levels by clipping the signal peaks. The ALC and/or Limiter can be disabled through the MPU serial interface.
C In
Lim Out
Gt
-11 -23 - -
-10.12 -20.16 29 0.5
-9.0 -17 - -
dB
dB %
C In C In
Lim Out Lim Out
Zin ta
- -
16 3.0
- -
k ms
Release Time
C In
Lim Out
tr
-
13.5
-
ms
Expander to Compressor Crosstalk Tx Data Mute
Rx Audio In C In
Lim Out Lim Out
CT Me
- -
-43.6 -76
- -
dB dB
ALC Dynamic Range ALC Output Level Limiter Output Level
C In C In C In
Lim Out Lim Out Tx Out
DR ALCout Vlim
- - - -
-18 to 2.5 -16 -11.4 0.8
- - - -
dBV dBV Vpp
MOTOROLA RF/IF DEVICE DATA
9
MC13109A
ELECTRICAL CHARACTERISTICS (continued) Splatter Amplifier The Splatter Amplifier is an inverting rail-to-rail output operational amplifier with the non-inverting input terminal connected to the internal VB half supply reference. External resistors and capacitors can be connected to set the gain and frequency response. The "Spl Amp In" input is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25C, fin = 1.0 kHz, External resistors Set for Gain of 1.) Characteristic Open Loop Gain Gain Bandwidth Maximum Output Swing Condition - - RL = 10 k Input Pin Spl Amp In Spl Amp In Spl Amp In Measure Pin Tx Out Tx Out Tx Out Symbol AVOL GBW VOmax Min - - - Typ 60 100 VCC - 0.3 Max - - - Unit dB kHz Vpp
Tx Audio Path Recommendation The recommended configuration for the Tx Audio path includes setting the Microphone Amplifier gain to 16 dB using the external gain setting resistors and setting the Splatter Amplifier gain to 9.0 dB using the external gain setting resistors. PLL Voltage Regulator The PLL supply voltage is regulated to a nominal of 2.2 V. The "VCC Audio" pin is the supply voltage for the internal voltage regulator. The "PLL Vref " pin is the 2.2 V regulated output voltage. Two capacitors with 10 F and 0.01 F values must be connected to the "PLL Vref " pin to filter and stabilize this regulated voltage. The voltage regulator provides power for the 2nd LO, Rx and Tx PLL's, and MPU Interface. The voltage regulator can also be used to provide a regulated supply voltage for external IC's. Rx and Tx PLL loop
(Test Conditions: VCC = 2.6 V, TA = 25C.) Characteristic Output Voltge Level Line Regulation Load Regulation Condition VCC = 2.6 V, OL= 0 mA IL = 0 mA, VCC = 2.6 to 5.5 V VCC = 2.6 V, IL = 0 to 1.0 mA Input Pin - VCC VCC
performance are independent of the power supply voltage when the voltage regulator is used. The voltage regulator requires about 200 mV of "headroom". When the power supply decreases to within about 200 mV of the output voltage, the regulator will go out of regulation but the output voltage will not turn off. Instead, the output voltage will maintain about a 200 mV delta to the power supply voltage as the power supply voltage continues to decrease. The "PLL Vref" pin can be connected to "VCC Audio" by the external wiring if voltage higher than 2.2 V is required. But it should not be connected to other supply except "VCC Audio". The voltage regulator is "on" in the Active and Rx modes. In the Standby and Inactive modes, the voltage regulator is turned off to reduce current drain and the "PLL Vref" pin is internally connected to "VCC Audio" (i.e., the supply voltage is maintained but is now unregulated).
Measure Pin VCC PLL VCC PLL VCC PLL
Symbol Vout Regline Regload
Min - - -40
Typ 2.2 3.66 -2.28
Max - 40 -
Unit V mV mV
10
MOTOROLA RF/IF DEVICE DATA
MC13109A
ELECTRICAL CHARACTERISTICS (continued) Low Battery Detect An external resistor divider is connected to the "Ref" input pin to set the threshold for the low battery detect. The voltage at the "Ref" input pin is compared to an internal 1.23 V
(Test Conditions: VCC = 2.6 V, TA = 25C.) Characteristic Average Threshold Voltage Hysteresis Input Current Output High Voltage Output Low Voltage Condition Take average of rising and falling threshold - Vin = 1.6 V Vref = 1.6, RL = 3.9 k Vref = 0.9, RL = 3.9 k Input Pin Ref Ref - Ref Ref Measure Pin Ref/ BD Out Ref/ BD Out Ref BD Out BD Out Symbol Threshold Hys Iin VOH VOL Min - - - VCC - 0.1 - Typ 1.23 2.0 12.33 2.59 0.6 Max - - 50 - 0.4 Unit V mV nA V V
Bandgap reference voltage. The "BD Out" pin is open collector and requires and external pull-up resistor to VCC.
Figure 3. Data Amp Operation
Data Amp Data Signal Hysteresis
Data Amp Output
MOTOROLA RF/IF DEVICE DATA
11
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PIN FUNCTION DESCRIPTION
48-TQFP Pin 1 2 3 52-QFP Pin 1 2 3 Symbol Type - Description LO2 In LO2 Out These pins form the PLL reference oscillator when connected to an external parallel-resonant crystal (10.24 MHz typical). The reference oscillator is also the second Local Oscillator (LO2) for the RF receiver. Voltage Regulator output pin. The internal voltage regulator provides a stable power supply voltage for the Rx and Tx PLL's and can also be used as a regulated supply voltage for the other IC's. PLL Vref Supply 4 4 Rx PD Output Three state voltage output of the Rx Phase Detector. This pin is either "high", "low", or "high impedance" depending on the phase difference of the phase detector input signals. During lock, very narrow pulses with a frequency equal to the reference frequency are present. This pin drives the external Rx PLL loop filter. It is important to minimize the line length and capacitance of this pin. Ground pin for PLL section of IC. 5 6 5 6 Gnd PLL Tx PD Gnd Output Three state voltage output of the Tx Phase Detector. This pin is either "high", "low", or "high impedance" depending on the phase difference of the phase detector input signals. During lock, very narrow pulses with a frequency equal to the reference frequency are present. This pin drives the external Tx PLL loop filter. It is important to minimize the line length and capacitance on this pin. Expander rectifier filter capacitor pin. Connect capacitor to VCC. 7 8 7 8 E Cap - Tx VCO Input Transmit divide counter input which is driven by an ac coupled external transmit loop VCO. The minimum signal level is 200 mVpp @ 80.0 MHz. This pin also functions as the test mode input for the counter tests. 9 10 11 9 10 11 Data EN Clk Input Microprocessor serial interface input pins for programming various counters and control functions. Microprocessor Clock Output which is derived from the 2nd LO crystal oscillator and a programmable divider. It can be used to drive a microprocessor and thereby reduce the number of crystals required in the system design. The driver has an internal resistor in series with the output which can be combined with an external capacitor to form a low pass filter to reduce radiated noise on the PCB. This output also functions as the output for the counter test modes. This pin indicates when the internal latches may have lost memory due to a power glitch. 12 12 Clk Out Output N/A 13 14 15 Status Out CD Out/ Hardware Interrupt BD Out DA Out SA Out SA In Output Output/ Input Output Output Output Input Dual function pin; 1) Carrier detect output (open collector with external 100 k pull-up resistor. 2) Hardware interrupt input which can be used to "wake-up" from Inactive Mode. Low battery detect output (open collector with external pull-up resistor). 14 15 16 17 18 19 20 21 22 23 24 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Data amplifier output (open collector with internal 100 k pull-up resistor). Speaker amplifier output. Speaker amplifier input (ac coupled). Expander output. E Out Output VCC Audio DA In Supply Input VCC supply for audio section. Data amplifier input (ac coupled). Pre-Amp Out Rx Audio In Det Out RSSI N/A Output Input Pre-amplifier output for connection of pre-amplifier feedback resistor. Rx audio input to pre-amplifier (ac coupled). Audio output from FM detector. Output - - - Receive signal strength indicator filter capacitor. Not used. N/A 25 26 27 28 Q Coil A quad coil or ceramic discriminator are connected to this pin. VCC supply for RF receiver section. IF amplifier/limiter capacitor pins. VCC RF Lim C2 Lim C1 Supply -
MC13109A
12
MOTOROLA RF/IF DEVICE DATA
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PIN FUNCTION DESCRIPTION (continued)
Type Input Gnd 48-TQFP Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 52-QFP Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Symbol Lim In Description Signal input for IF amplifier/limiter. Gnd RF Ground pin for RF section of the IC. Second mixer output. Second mixer input. Mix2 Out Mix2 In VB Output Input - Internal half supply analog ground reference. First mixer output. Mix1 Out Mix1 In2 Mix1 In1 Output Input Input - - Negative polarity first mixer input. Positive polarity first mixer input. LO1 In LO1 Out Tank elements for 1st LO multivibrator oscillator are connected to these pins. 1st LO varactor control pin. Vcap Ctrl Gnd Audio Tx In Gnd Ground for audio section of the IC. Input Tx path input to Microphone Amplifier (ac coupled). Microphone amplifier output. Amp Out C In Output Input - Compressor input (ac coupled). C Cap Compressor rectifier filter capacitor pin. Connect capacitor to VCC. Tx path limiter output. Lim Out Output Input Spl Amp In Tx Out Ref Splatter amplifier input (ac coupled). Tx path audio output. Output Input - Reference voltage input for low battery detect. Not used. N/A N/A
MC13109A
Power Supply Voltage This circuit is used in a cordless telephone handset and base unit. The handset is battery powered and can operate on two or three NiCad cells or on 5.0 V power.
PLL Frequency Synthesizer General Description Figure 4 shows a simplified block diagram of the programmable universal dual phase locked loop (PLL). This dual PLL is fully programmable through the MCU serial interface and supports most country channel frequencies including USA (25 ch), France, Spain, Australia, Korea, New Zealand, U.K., Netherlands and China (see channel frequency tables in Appendix A). The 2nd local oscillator and reference divider provide the reference frequency for the Rx and Tx PLL loops. The
programmed divider value for the reference divider is selected based on the crystal frequency and the desired Rx and Tx reference frequency values. Additional divide by 25 and divide by 4 blocks are provided to allow for generation of the 1.0 kHz and 6.25 kHz reference frequencies required for the U.K. The 14-Bit Tx counter is programmed for the desired transmit channel frequency. The 14-Bit Rx counter is programmed for the desired first local oscillator frequency. All counters power up in the proper default state for USA channel #6 and for a 10.24 MHz reference frequency crystal. Internal fixed capacitors can be connected to the tank circuit of the 1st LO through microprocessor control to extend the sensitivity of the 1st LO for U.S. 25 channel operation.
MOTOROLA RF/IF DEVICE DATA
13
MC13109A
Figure 4. Dual PLL Simplified Block Diagram
14-b Programmable Tx Counter U.K. Base Tx Ref LO2 In 1, 1 LO2 Out 2, 2 12-b / 25 Programmable /4 Reference /1 Counter U.K. Handset U.K. Base Rx Ref U.K. Handset Rx Phase Detector Rx PD 4, 4 Vcap Ctrl 39, 42 LO1 In 14-b Programmable Rx Counter 1st LO 37, 40 LO1 Out 38, 41 LPF Tx Phase Detector Tx VCO 8, 8 Tx PD 6, 6 LPF Tx VCO
LO2
ELECTRICAL CHARACTERISTICS (VCC = 2.6 V, TA = 25C)
Characteristic PLL PIN DC Input Voltage Low - Data Clk EN Hardware Int. Data Clk EN Data Clk EN Data Clk EN Data Clk EN Rx PD Tx PD Rx PD Tx PD Rx PD Tx PD Rx PD Tx PD Rx PD Tx PD - Data Clk EN Rx PD Tx PD VIL - - 0.3 V Condition Measure Pin Symbol Min Typ Max Unit
Input Voltage High
-
VIH
"PLL Vref" - 0.3 -5.0
-
"VCC Audio"
V
Input Current Low
Vin = 0.3 V
IIL
-3.0
-
A
Input Current High
Vin = (VCC Audio) - 0.3 -
IIH
-
0.6
5.0
A
Hysteresis Voltage
Vhys
-
1.0
-
V
Output Current High Output Current Low Output Voltage Low Output Voltage High Tri-State Leakage Current Input Capacitance
- - IIL = 0.7 mA IIH = - 0. 7mA V = 1.2 V
IOH IOL VOL VOH IOZ Cin
- 0.7 - (PLL Vref)* 0.8 - 50 -
- - - - - -
- 0.7 - (PLL Vref)* 0.2 - 50 8.0
mA mA V V nA pF
Output Capacitance
-
Cout
-
-
8.0
pF
14
MOTOROLA RF/IF DEVICE DATA
MC13109A
ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.6 V, TA = 25C)
Characteristic PLL PIN INTERFACE EN to Clk Setup Time Data to Clk Setup Time Hold Time Recovery Time Input Pulse Width Input Rise and Fall Time - - - - - - EN, Clk Data, Clk Data, Clk EN, Clk EN, Clk Data Clk EN - tsuEC tsuDC th trec tw tr, tf 200 100 90 90 100 - - - - - - - - - - - - 9.0 ns ns ns ns ns s Condition Measure Pin Symbol Min Typ Max Unit
MPU Interface Power-Up Delay PLL LOOP 2nd LO Frequency "Tx VCO" Input Frequency
90% of PLL Vref to Data, Clk, EN
tpuMPU
-
100
-
s
- Vin = 200 mVpp
LO2 In LO2 Out Tx VCO
fLO ftxmax
- -
- -
12 80
MHz MHz
PLL I/O Pin Specifications The 2nd LO, Rx and Tx PLL's and MPU serial interface are normally powered by the internal voltage regulator at the "PLL Vref" pin. The "PLL Vref" pin is the output of a voltage regulator which is powered from the "VCC Audio" power supply pin. Therefore, the maximum input and output levels for most PLL I/O pins (LO2 In, LO2 Out, Rx PD, Tx PD, Tx VCO) is the regulated voltage at the "PLL Vref" pin. The ESD protection diodes on these pins are also connected to "PLL Vref". Internal level shift buffers are provided for the pins (Data, Clk, EN, Clk Out) which connect directly to the microprocessor. The maximum input and output levels for these pins is VCC. Figure 5 shows a simplified schematic of the PLL I/O pins. Figure 5. PLL I/O Pin Simplified Schematics
PLL Vref (2.2 V) VCC Audio (2.0 to 5.5 V) PLL Vref (2.2 V) VCC Audio (2.0 to 5.5 V)
Figure 6. Data and Clock Timing Requirement
tr 90% Data, Clk, EN 50% Data tsuDC th 50% Clk 10% tf
I/O
In 2.0 A
1.0 k
Out
LO2 In, LO2 Out, Rx PD, Tx PD and Tx VCO Pins
Data, Clk, and EN Pins
Clk Out Pin
After data is loaded into the shift register, the data is latched into the appropriate latch register using the "EN" pin. This is done in two steps. First, an 8-Bit address is loaded into the shift register and latched into the 8-Bit address latch register. Then, up to 16-Bits of data is loaded into the shift register and latched into the data latch register specified by the address that was previously loaded. Figure 7 shows the timing required on the EN pin. Latching occurs on the negative EN transition.
Microprocessor Serial Interface The "Data", "Clk", and "EN" pins provide an MPU serial interface for programming the reference counters, the transmit and receive channel divider counter and various control functions. The "Data" and "Clk" pins are used to load data into the shift register. Figure 6 shows "Data" and "Clk" pin timing. Data is clocked on positive clock transitions.
MOTOROLA RF/IF DEVICE DATA
15
MC13109A
Figure 7. Enable Timing Requirement modes; Inactive, Standby, Rx, and Active Modes. Data can be loaded into the shift registers and latched into the latch registers in any of the operating modes. Figure 9. Microprocessor Serial Interface Power-Up Delay
2.0 V Previous Data Latch VCC tpuMPU
50% Clk tsuEC
Last Clock
50% trec 50%
First Clock
50% EN
The state of the EN pin when clocking data into the shift register determines whether the data is latched into the address register or a data register. Figure 8 shows the address and data programming diagrams. In the data programming mode, there must not be any clock transitions when "EN" is high. The clock can be in a high state (default high) or a low state (default low) but must not have any transitions during the "EN" high state. The convention in these figures is that latch bits to the left are loaded into the shift register first. Figure 8. Microprocessor Interface Programming Mode Diagrams
Data MSB 8-Bit Address LSB Latch EN Data Address Register Programming Mode MSB 16-Bit Data LSB Latch EN Data Register Programming Mode
Data, Clk, EN
Status Out This is a digital output which indicates whether the latch registers have been reset to their power-up default values. Latch power-up default values are given in Figure 28. If there is a power glitch or ESD event which causes the latch registers to be reset to their default values, the "Status Out" pin will indicate this to the MPU so it can reload the correct information into the latch registers.
The MPU serial interface is fully operational within 100 s after the power supply has reached its minimum level during power-up (See Figure 9). The MPU Interface shift registers and data latches are operational in all four power saving
16
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Figure 10. Status Out Operation
Status Latch Register Bits Status Out Logic Level Latch bits not at power-up default valueAAAAAA 0 Latch bits at power-up default value
1
Data Registers Figure 11 shows the data latch registers and addresses which are used to select each of these registers. Latch bits to the left (MSB) are loaded into the shift register first. The LSB bit must always be the last bit loaded into the shift register. "Don't Care" bits can be loaded into the shift register first if 8-Bit bytes of data are loaded.
MOTOROLA RF/IF DEVICE DATA
MC13109A
Figure 11. Microprocessor Interface Data Latch Registers
Latch Address
MSB 14-Bit Tx Counter LSB
1. (00000001)
Tx Counter Latch
MSB
14-Bit Rx Counter
LSB
2. (00000010)
Rx Counter Latch
U.K. Handset Select U.K. Base Select
MSB
12-Bit Reference Counter
LSB
3. (00000011)
Reference Counter Latch
ALC Disable Not Used Limiter Disable Clk Disable MPU Clk1 MPU Clk0 14-Bit Volume Control Stdby Mode Rx Mode Tx Mute Rx Mute SP Mute
MSB
LSB
4. (00000100)
Mode Control Latch
MSB
5-Bit CD Threshold Control
LSB
5. (00000101)
Threshold Control Latch
6. (00000110)
4-Bit Test Mode
3-Bit 1st LO Capacitor Selection
7. (00000111)
7-Bit Auxillary Latch
Reference Frequency Selection The "LO2 In" and "LO2 Out" pins form a reference oscillator when connected to an external parallel-resonant crystal. The reference oscillator is also the second local oscillator for the RF Receiver. Figure 12 shows the relationship between different crystal frequencies and reference frequencies for cordless phone applications in various countries.
Figure 12. Reference Frequency and Reference Divider Values
Crystal Frequency 10.24 MHz 10.24 MHz 11.15 MHz
ReferenceAAAAA U.K. Base/ Divider Handset Reference Value Divider Frequency 2048 1024 2230 2400 1784 446 446 1 4 1 1 1 4 5.0 kHz 2.5 kHz 5.0 kHz 5.0 kHz
12.00 MHz 11.15 MHz 11.15 MHz 11.15 MHz
Reference Counter Figure 13 shows how the reference frequencies for the Rx and Tx loops are generated. All countries except U.K. require that the Tx and Rx reference frequencies be identical. In this case, set "U.K. Base Select" and "U.K. Handset Select" bits to "0". Then the fixed divider is set to "1" and the Tx and Rx reference frequencies will be equal to the crystal oscillator frequency divided by the programmable reference counter value. The U.K. is a special case which requires a different reference frequency value of Tx and Rx. For U.K. base operation, set "U.K. Base Select" to "1". For U.K. handset operation, set "U.K. Handset Select" to "1". The Netherlands is also a special case since a 2.5 kHz reference frequency is used for both the Tx and Rx reference and the total divider value required is 4096 which is larger than the maximum divide value available from the 12-Bit reference divider (4095). In this case, set "U.K. Base Select" to "1" and set "U.K. Handset Select" to "1". This will give a fixed divide by 4 for both the Tx and Rx reference. Then set the reference divider to 1024 to get a total divider of 4096. Mode Control Register Power saving modes, mutes, disables, volume control, and microprocessor clock output frequency are all set by the Control Register. Operation of the Control Register is explained in Figures 14 through 21.
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6.25 kHz 6.25 kHz 1.0 kHz 25
MOTOROLA RF/IF DEVICE DATA
17
MC13109A
Figure 13. Reference Register Programming Mode
U.K. Base Tx Reference Frequency LO2 In LO2 LO2 Out / 25 12-b Programmable /4 Reference Counter /1 U.K. Handset U.K. Base Rx Reference Frequency U.K. Handset
U.K. Handset Select 0 0 1 1
U.K. Base Select 0 1 0 1
Tx Divider Value 1 25 4 4
Rx Divider Value 1 4 25 4
Application All but U.K. and Netherlands U.K. Baseset U.K. Handset Netherlands Base and Handset
U.K. Handset Select
U.K. Base Select
MSB
12-Bit Reference Counter 14-Bit Reference Counter Latch
LSB
Figure 14. Control Register Bits
ALC Disable
Not Used
Limiter Disable
Clk Disable
MPU Clk1
MPU Clk0
MSB
4-Bit Volume Control
LSB
Stdby Mode
Rx Mode
Tx Mute
Rx Mute
SP Mute
Rx Mute
1 0 1 0
Receive Channel Muted Normal Operation Speaker Amp Muted Normal Operation
SP Mute
Power Saving Operating Modes When the MC13109A is used in a handset, it is important to conserve power in order to prolong battery life. There are five modes of operation; Active, Rx, Standby, Interrupt and Inactive. In Active Mode, all circuit blocks are powered. In Rx mode, all circuitry is powered down except for those circuit
18
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A A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAA A A AAAAAAAAAA A AA AA AAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAA AAAAAAAAAA A AA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAA
ALC Disable 1 0 1 0 1 0 1 0 Automatic Level Control Disabled Normal Operation Limiter Disabled Normal Operation Limiter Disable Clock Disable Tx Mute MPU Clock Output Disabled Normal Operation Transmit Channel Muted Normal Operation
Figure 15. Mute and Disable Control Bit Descriptions
sections needed to receive a transmission from the base. In the Standby and Interrupt Modes, all circuitry is powered down except for the circuitry needed to provide the clock output for the microprocessor. In Inactive Mode, all circuitry is powered down except the MPU interface. Latch memory is maintained in all modes. Figure 16 shows the control register bit values for selection of each power saving mode and Figure 17 show the circuit blocks which are powered in each of these operating mode. Figure 16. Power Saving Mode Selection
Rx Mode Bit 0 1 0 1 1 "CD Out/Hardware Interrupt" Pin X X X
Stdby Mode Bit 0 0 1 1 1
Power Saving Mode Active Rx
Standby Inactive Inactive
1 or High Impedance 0
MOTOROLA RF/IF DEVICE DATA
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Figure 17. Circuit Blocks Powered During Power Saving Modes
Active X X X X X X X X X X X X X Rx X X X X X X X X X X X1 X X X Circuit Blocks Standby Inactive X1 X "PLL Vref" Regulated Voltage MPU Interface 2nd LO Oscillator MPU Clock Output RF Receiver 1st LO VCO Rx PLL Carrier Detect Data Amp Low Battery Detect Tx PLL Rx Audio Path Tx Audio Path
NOTE: 1. In Standby and Inactive Modes, "PLL Vref" remains powered but is not regulated. It will fluctuate with VCC.
MC13109A
Inactive Mode Operation and Hardware Interrupt In some handset applications it may be desirable to power down all circuitry including the microprocessor (MPU). First put the MC13109A into the Inactive mode, which turns off the MPU Clock Output (see Figure 18), and then disable the microprocessor. In order to give the MPU adequate time to power down, the MPU Clock output remains active for a minimum of one reference counter cycle (about 200 s) after the command is given to switch into the "Inactive" mode. An external timing circuit should be used to initiate the turn-on sequence. The "CD Out" pin has a dual function. In the Active and Rx modes it performs the carrier detect function. In the
Standby and Inactive modes the carrier detect circuit is disabled and the "CD Out" pin is in a "High" state due to the external pull-up resistor. In the Inactive mode the "CD Out" pin is the input for the hardware interrupt function. When the "CD Out" pin is pulled "low" by the external timing circuit, the MC13109A switches from the Inactive to the Interrupt mode thereby turning on the MPU Clock Output. The MPU can then resume control of the combo IC. The "CD Out" pin must remain low until the MPU changes the operating mode from Interrupt to Standby, Active or Rx modes.
Figure 18. Hardware Interrupt Operation
Mode Active/Rx Inactive MPU Initiates Inactive Mode CD Out Low CD Turns Off MPU Clock Out Delay after MPU selects Inactive Mode to when CD turns off "MPU Clock Out" remains active for a minimum of one count of reference counter after "CD Out/Hardware Interrupt" pin goes high External Timer Pulls Pin Low Interrupt Standby/Rx/Active MPU Initiates Mode Change
EN CD Out/Hardware Interrupt
Timer Output Disabled
MOTOROLA RF/IF DEVICE DATA
19
MC13109A
"Clk Out" Divider Programming The "Clk Out" pin is derived from the 2nd local oscillator and can be used to drive a microprocessor, thereby reducing the number of crystals required. Figure 19 shows the relationship between the crystal frequency and the clock output for different divider values. Figure 20 shows the "Clk Out" register bit values. Figure 19. Clock Output Values
Clock Output Divider 3 5
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Crystal Frequency 10.24 MHz 11.15 MHz 2 10 5.120 MHz 5.575 MHz 6.000 MHz 3.413 MHz 3.717 MHz 4.000 MHz 2.048 MHz 2.230 MHz 2.400 MHz 1.024 MHz 1.115 MHz 12.00 MHz 1.200 MHz
MPU "Clk Out" Power-Up Default Divider Value The power-up default divider value is "divide by 10". This provides an MPU clock of about 1.0 MHz after initial power-up. The reason for choosing this relatively low clock frequency after intial power-up is that some microprocessors that operate down to a 2.0 V power supply have a maximum clock frequency of 1.0 MHz. After initial power-up, the MPU can change the clock divider value to set the clock to the desired operating frequency. Special care has been taken in the design of the clock divider to ensure that the transition between one clock divider value and another is "smooth" (i.e., there will be no narrow clock pulses to disturb the MPU).
Figure 20. Clock Output Divider
Clk Out Bit #2 0 1 0 1
Clk Out Bit #1 0 0 1 1
Clk Out Divider Value 2 3 5
MPU "Clk Out" Radiated Noise on Circuit Board The clock line running between the MC13109A and the microprocessor has the potential to radiate noise which can cause problems in the system especially if the clock is a square wave digital signal with large high frequency harmonics. In order to minimize radiated noise, a 1.0 k resistor is included on-chip in-series with the "Clk Out" output driver. A small capacitor can be connected to the "Clk Out" line on the PCB to form a single pole low pass filter. This filter will significantly reduce noise radiated from the "Clk Out" line. Volume Control The volume control can be programmed in 2.0 dB gain steps from -14 dB to 16 dB. The power-up default value is 0 dB.
10
Figure 21. Volume Control
Volume Control Bit #3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Volume Control Bit #2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Volume Control Bit #1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Volume Control Bit #0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Volume Control # 0 1 2 3 4 5 6 7 8 9
Gain/Attenuation Amount -14 dB -12 dB -10 dB
- 8.0 dB - 6.0 dB - 4.0 dB - 2.0 dB 0 dB
2.0 dB 4.0 dB 6.0 dB 8.0 dB 10 dB 12 dB 14 dB 16 dB
10 11
12 13 14 15
Gain Control Register The gain control register contains bits which control the Carrier Detect threshold. Operation of these latch bits are explained in Figures 22 and 23.
Figure 22. Gain Control Latch Bits
MSB
5-Bit CD Threshold Control
LSB
20
MOTOROLA RF/IF DEVICE DATA
AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A A A A A AAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Carrier Detect Threshold Programming The "CD Out" pin will give an indication to the microprocessor if a carrier signal is present on the selected channel. The nominal value and tolerance of the carrier
CD Bit #4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CD Bit #3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 CD Bit #2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
MOTOROLA RF/IF DEVICE DATA Figure 23. Carrier Detect Threshold Control
CD Bit #1
MC13109A
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
detect threshold is given in the carrier detect specification section of this document. If a different carrier detect threshold value is desired, it can be set through the MPU interface as shown in Figure 23 below.
CD Bit #0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CD Control #
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
0
Carrier Detect Threshold
- 2.0 dB
- 3.0 dB
- 4.0 dB
- 5.0 dB
- 6.0 dB
- 8.0 dB
- 9.0 dB
-1.0 dB
-7.0 dB
- 20 dB
-10 dB
-12 dB
-13 dB
-14 dB
-15 dB
-16 dB
-17 dB
-18 dB
-19 dB
-11 dB
9.0 dB
8.0 dB
7.0 dB
6.0 dB
5.0 dB
4.0 dB
3.0 dB
2.0 dB
1.0 dB
10 dB
11 dB
0 dB
21
MC13109A
Auxiliary Register The auxiliary register contains a 3-Bit 1st LO Capacitor Selection latch and a 4-Bit Test Mode latch. Operation of these latch bits are explained in Figures 24, 25 and 26. Figure 24. Auxiliary Register Latch Bits Figure 25. First LO Schematic
MSB 4-Bit Test Mode LSB MSB 3-Bit 1st LO LSB Capacitor Selection Vcap Ctrl Varactor 42 LO1 In Cext 40 LO1 Out 41 Lext
circuit to change the 1st LO sensitivity. Internal switches and capacitors are provided to enable microprocessor control over internal fixed capacitor values. Figure 25 shows the schematic of the 1st LO tank circuit. Figure 26 shows the latch control bit values.
First Local Oscillator Capacitor Selection for 25 Channel U.S. Operation There is a very large frequency difference between the minimum and maximum channel frequencies in the proposed 25 Channel U.S. standard. The sensitivity of the 1st LO is not large enough to accommodate this large frequency variation. Fixed capacitors can be connected across the 1st LO tank
Internal Capacitor 1st LO Varactor
A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A A A A AA AA A A A AAAA A A AAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AA A A A AAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Figure 26. 1st LO Capacitor Select for U.S. 25 Channels
1st LO Cap. Select 0 0 1 2 3 4 U.S. Base Channels 16 - 25 - U.S. Handset Channels - Varactor Value over 0.5 to 2.2 V Range 10 - 6.4 pF 10 - 6.4 pF 10 - 6.4 pF 10 - 6.4 pF 10 - 6.4 pF 1st LO Cap. Bit 2 0 0 0 0 0 1 1st LO Cap. Bit 1 0 0 0 1 1 0 1st LO Cap. Bit 0 0 0 1 0 1 0 External Capacitor Value 27 pF 33 pF 27 pF 27 pF 33 pF 33 pF External Inductor Value 0.47 H 0.47 H 0.47 H 0.47 H 0.47 H 0.47 H 16 - 25 - - 1-6 7 - 15 - - 1-6 7 - 15 10 - 6.4 pF
22
MOTOROLA RF/IF DEVICE DATA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAA A A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAA AAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAA A AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Figure 27. Test Mode Description
TM # 0 1 2 3 4 5 6 7 8 9 TM 3 0 0 0 0 0 0 0 0 1 1 1 TM 2 0 0 0 0 1 1 1 1 0 0 0 TM 1 0 0 1 1 0 0 1 1 0 0 1 TM 0 0 1 0 1 0 1 0 1 0 1 0 Counter Under Test or Test Mode Option "Tx VCO" Input Signal >200 mVpp 0 to 2.2 V 0 to 2.2 V 0 to 2.2 V 0 to 2.2 V 0 to 2.2 V "Clk Out" Output Expected - Normal Operation Rx Counter, upper 6 Rx Counter, lower 8 Rx Prescaler Input Frequency/64 See Note Below Input Frequency/4 Tx Counter, upper 6 Tx Counter, lower 8 Tx Prescaler Input Frequency/64 See Note Below >200 mVpp 0 to 2.2 V 0 to 2.2 V N/A N/A Input Frequency/4 Reference Counter Divide by 4, 25 Input Frequency/Reference Counter Value Input Frequency/100 AGC Gain = 10 Option AGC Gain = 25 Option - - 10
NOTE: To determine the correct output, look at the lower 8 bits in the Rx or Tx register (Divisor (7;0). If the value of the divisor is > 16, then the output divisor value is Divisor (7;2) (the upper 6 bits of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3 of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60).
MC13109A
Test Modes Test Mode Control latch bits enable independent testing of internal counters and set AGC Gain Options. In test mode, the "Tx VCO" input pin is multiplexed to the input of the counter under test and the output of the counter under test is multiplexed to the "Clk Out" output pin so that each counter can be individually tested. Make sure test mode bits are set to "0" for normal operation. Test mode operation is described in Figure 27. During normal operation and when testing the Tx Prescaler, the "Tx VCO" input can be a minimum of 200 mVpp at 80 MHz and should be ac coupled. For other test modes, input signals should be standard logic levels of 0 to 2.2 V and a maximum frequency of 16 MHz.
Power-Up Defaults for Control and Counter Registers When the IC is first powered up, all latch registers are initialized to a defined state. The MC13109A is initially placed in the Rx mode with all mutes active and nothing disabled. The reference counter is set to generate a 5.0 kHz reference frequency from a 10.24 MHz crystal. The MPU clock output divider is set to 10 to give the minimum clock output frequency. The Tx and Rx latch registers are set for USA Channel Frequency #21. Figure 28 shows the initial power-up states for all latch registers.
AAAA AA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AA AA A AA A A AAAA AA A AA A AA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AA AA A AA A A A AA A AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AA AA A AA A A A AA A AA A AA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Figure 28. Latch Register Power-Up Defaults
MSB LSB Register Tx Count 9965 7215 2048 N/A N/A N/A 15 - - - - - - 14 - - - 0 - - 13 1 0 0 0 - - 12 0 1 0 0 - - 11 0 1 1 0 - - 10 1 1 0 1 - - 9 1 0 0 1 - - 8 0 0 0 0 - - 7 1 0 0 1 - - 6 1 0 0 1 - 0 5 1 1 0 1 - 0 4 0 0 0 0 1 0 3 1 1 0 1 0 0 2 1 1 0 1 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 Rx Ref Mode Gain TM
MOTOROLA RF/IF DEVICE DATA
23
MC13109A
Figure 29. ICC versus VCC at Active Mode
8.0 I CC , SUPPLY CURRENT (mA) I CC , SUPPLY CURRENT (mA) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 2.5 3.0 3.5 4.0 4.5 5.0 2.5 2.5 3.0 3.5 4.0 4.5 5.0 5.0 4.5 4.0 3.5 3.0
Figure 30. ICC versus VCC at Receive Mode
VCC, SUPPLY VOLTAGE (V)
VCC, SUPPLY VOLTAGE (V)
Figure 31. ICC versus VCC at Standby Mode
1.2 I CC , SUPPLY CURRENT (mA) I CC , SUPPLY CURRENT ( A) 1.0 0.8 0.6 0.4 0.2 0 2.5 80 70 60 50 40 30 20 10 3.0 3.5 4.0 4.5 5.0 0 2.5
Figure 32. ICC versus VCC at Inactive Mode
3.0
3.5
4.0
4.5
5.0
VCC, SUPPLY VOLTAGE (V)
VCC, SUPPLY VOLTAGE (V)
Figure 33. RSSI Output versus RFin
1.6 1.4 RSSI OUTPUT (dB) 1.2 1.0 0.8 0.6 0.4 0.2 0 -120 -100 -80 -60 -40 -20 0 RECOVERED AUDIO (V) 300 250 200 150 100
Figure 34. Recovered Audio/THD versus fDEV
6.0 R22 = 12 k Recovered Audio 5.0 4.0 3.0 2.0 THD 50 0 1.0 1.0 0 9.0 THD (%)
2.0
3.0
4.0
5.0
6.0
7.0
8.0
RFin, RF INPUT (dBm)
fDEV, DEVIATION, (kHz)
24
MOTOROLA RF/IF DEVICE DATA
MC13109A
Figure 35. Typical Expander Response
COMPRESSOR LEVEL OUTPUT, LIM OUT (dBV) 10 0 EXPANDER, E OUT (dBV) -10 -20 -30 -40 -50 -60 -70 -35 -30 -25 -20 -15 -10 -5.0 0 0 -10 -20 -30 -40 -50 -60 -80 ACL "Off" ACL "On"
Figure 36. Typical Compressor Response
-70
-60
-50
-40
-30
-20
-10
0
Rx AUDIO IN (dBV)
COMPRESSOR, Cin LEVEL INPUT (dBV)
Figure 37. First Mixer Third Order Intercept Performance
0 0
Figure 38. Second Mixer Third Order Intercept Performance
MIXER OUTPUT (dBm)
-40
MIXER OUTPUT (dBm) -70 -60 -50 -40 -30 -20 -10 0
-20
-20
-40
-60
-60
-80 -80
-80 -90
-80
-70
-60
-50
-40
-30
-20
-10
0
MIXER1 IN (dBm)
MIXER2 IN (dBm)
MOTOROLA RF/IF DEVICE DATA
25
MC13109A
APPENDIX A - MEASUREMENT OF COMPANDOR ATTACK/DECAY TIME
This measurement definition is based on EIA/CCITT recommendations. Compressor Attack Time For a 12 dB step up at the input, attack time is defined as the time for the output to settle to 1.5X of the final steady state value. Compressor Decay Time For a 12 dB step down at the input, decay time is defined as the time for the input to settle to 0.75X of the final steady state value. Expander Attack For a 6.0 dB step up at the input, attack time is defined as the time for the output to settle to 0.57X of the final steady state value. Expander Decay For a 6.0 dB step down at the input, decay time is defined as the time for the output to settle to 1.5X of the final steady state value.
12 dB Input Input
6.0 dB
0 mV
0 mV
Attack Time
Decay Time
Attack Time
Decay Time
1.5X Final Value 0.57X Final Value Output Output 1.5X Final Value 0.75X Final Value
0 mV
0 mV
26
MOTOROLA RF/IF DEVICE DATA
MC13109A
OUTLINE DIMENSIONS
FB SUFFIX PLASTIC PACKAGE CASE 848B-04 (QFP-52) ISSUE C
B B
L
39 40
27 26 S
-A-, -B-, -D- DETAIL A F D D 0.05 (0.002) A-B V C A-B
S S
DETAIL A -A- L -B- B
H A-B
S
J
N
M
0.20 (0.008)
0.20 (0.008)
M
BASE METAL
52 1 13
14
D 0.02 (0.008)
M
C A-B
S
D
S
SECTION B-B -D- 0.20 (0.008)
M
B H A-B V
S
D
S
0.05 (0.002) A-B 0.20 (0.008) C E -H-
DATUM PLANE M
C A-B
S
D M_
S
DETAIL C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MILLIMETERS MIN MAX 9.90 10.10 9.90 10.10 2.10 2.45 0.22 0.38 2.00 2.10 0.22 0.33 0.65 BSC --- 0.25 0.13 0.23 0.65 0.95 7.80 REF 5_ 10_ 0.13 0.17 0_ 7_ 0.13 0.30 12.95 13.45 0.13 --- 0_ --- 12.95 13.45 0.35 0.45 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.009 0.015 0.079 0.083 0.009 0.013 0.026 BSC --- 0.010 0.005 0.009 0.026 0.037 0.307 REF 5_ 10_ 0.005 0.007 0_ 7_ 0.005 0.012 0.510 0.530 0.005 --- 0_ --- 0.510 0.530 0.014 0.018 0.063 REF
0.10 (0.004) H G M_ U_ -C-
SEATING PLANE DIM A B C D E F G H J K L M N Q R S T U V W X
R Q_ T W X DETAIL C K
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA RF/IF DEVICE DATA
27
MC13109A
OUTLINE DIMENSIONS
FTA SUFFIX PLASTIC PACKAGE CASE 932-02 (Thin QFP) ISSUE D DETAIL Y P
4X
0.200 (0.008) AB T-U Z 9 A1
48 37
A
1
36
-T- B B1
12 25
-U- V AE V1 AE
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350 (0.014). 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9 EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BASIC 0.050 0.150 0.090 0.200 0.500 0.700 12 _REF 0.090 0.160 0.250 BASIC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.007 0.011 0.053 0.057 0.007 0.009 0.020 BASIC 0.002 0.006 0.004 0.008 0.020 0.028 12 _REF 0.004 0.006 0.010 BASIC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
13
24
-Z- S1 -T-, -U-, -Z- S
4X
DETAIL Y 0.200 (0.008) AC T-U Z G 0.080 (0.003) AC
-AB- -AC- AD
BASE METAL
M_
TOP & BOTTOM
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
R
GAUGE PLANE
0.080 (0.003)
SECTION AE-AE
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28
CCCC EEEE CCCC EEEE CCCC
F D
M
N
J C E
0.250 (0.010)
AC T-U
S
Z
S
H DETAIL AD
W K X
Q_
Mfax is a trademark of Motorola, Inc. JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488
MC13109A/D MOTOROLA RF/IF DEVICE DATA

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